Current System-on-a-chip (SoC) designs contain increased levels of functional and structural complexities within a single system. With this integration of multiple design functionalities, various clock domains are introduced for different portions of the SoC. Verification of these Clock Domain Crossing (CDC) designs presents daunting challenges since there are issues related to transistor level analog effects. Traditional Register Transfer Level (RTL) functional simulation verification techniques are insufficient to identify these analog issues.
Known CDC related issues include metastability issues caused by setup and hold-time violations of flip-flops, jitter due to unpredictable delays across clock domains, functional issues due to convergence and divergences of crossover paths and functional issues due to divergence of metastable signals. Although static timing analysis (STA) is useful, it requires manual inspection, it assumes false paths, and it is prone to errors. Gate-level simulations, which are performed as a part of regular verification, may or may not find timing violations, depending upon timing constraints and the implementation. If a gate-level simulation finds a timing violation for any path of a CDC signal, one cannot be sure whether there are any other potential violations in various CDC paths. Fixing the design at these late stages is also very risky.
Various CDC verification approaches are known. These include using CDC electronic design automation (EDA) tools, which utilize formal verification techniques to find missing synchronizers, re-convergence of synchronized signals and divergence in crossover. System Verilog Assertions have been used to find CDC issues in simulation.
Most prior art approaches assume that there is no combinatorial logic in a domain crossing and in most cases combinatorial logic in a clock domain crossing is not recommended. However, if combinatorial logic in domain crossings is required to meet performance goals or for any other reason, it is important to insure that the glitches from the output of the combinatorial logic do not cause potential timing violations at the receiver.